1. Field of the Invention
The present invention relates to a communication system for carrying out digital data communication through encoding and decoding in an interleaving system, and a signal converter employed for the communication system.
2. Background of the Invention
In a digital data communication system, data signals which are transmitted from a transmission side to a receiving side may cause code errors. An interleaving system is known as a prevailing method of enabling normal communication upon occurrence of such code errors. This interleaving system is adapted to change the list of data signals which are lined up in a time-series manner in accordance with a certain constant rule, for transmitting the data signals. According to this system, therefore, it is considerably possible to decode the data signals on the receiving side also when burst errors are caused, in particular. When the data signals are interleaved on the transmission side, it is necessary to de-interleave the same on the receiving side in accordance with the rule employed in transmission, for restoring the original data list. For example, the satellite broadcasting system in Japan is one of the communication systems employing the interleaving system.
FIG. 15 is a block diagram showing a conventional de-interleaver. An interleaver is similar in structure to the de-interleaver shown in FIG. 15, and hence only the de-interleaver is now described, to omit redundant description. In this de-interleaver, de-interleaving is completed in the minimum unit (hereinafter referred to as "frame") of 2.sup.M by 2.sup.N with respect to positive integers M and N. In other words, one frame is formed by 2.sup.M by 2.sup.N bits.
A space for de-interleaving is formed by storage media 5a and 5b, which are addressable in a range of 1 to 2.sup.M by 2.sup.N so that 1-bit length data signals can be written in and read from the respective addresses. A counter circuit 2 repetitively counts the number of clock pulses which are inputted from a clock input terminal 1 synchronously with bitwise digital data signals within a range of 1 to 2.sup.M by 2.sup.N. Another counter circuit 3 repetitively counts the number of repetition of the counter circuit 2 counting 1 to 2.sup.M by 2.sup.N, in a range of 1 and 2. A signal selection circuit 4 which is connected with outputs of the two counter circuits 2 and 3 outputs address signals for addressing the storage media 5a and 5b on the basis of count values of the counter circuits 2 and 3.
A de-interleaving operation in this de-interleaver is now described. While one frame is formed by 64 by 32 bits (2048 bits) in the aforementioned satellite broadcasting system with M=6 and N=5, description is made on a de-interleaving operation with a frame structure of 8 by 4 bits (32 bits) with M=3 and N=2, for convenience of illustration.
Each of the storage media 5a and 5b forming two planes has an address space of 8 by 4 bits. These storage media 5a and 5b are hereinafter referred to as planes A and B respectively.
FIG. 16 shows timings of transmitted data signals DIN not yet de-interleaved and clocks CLK, and the transmission order of the data signals DIN. FIG. 17 shows timings of de-interleaved data signals DOUT and clocks CLK, and the transmission order of the data signals DOUT. As shown in these figures, the de-interleaving operation is adapted to sequence the data signals DIN, which are transmitted in the order of 0, 1, 2, 3, . . . , 30 and 31, as 0, 4, 8, 12, . . . , 27 and 31.
FIG. 18 shows addresses (for one plane) of each storage medium in the form of a matrix, for convenience of illustration (it is assumed that the planes A and B are identical to each other). FIG. 19 shows an order for storing data signals in the storage medium plane A in arbitrary K-th, (K+2)-th, (K+4)-th, . . . frames, where K represents an arbitrary integer. FIG. 20 shows an order for reading data signals from the storage medium plane B in the arbitrary K-th, (K+2)-th, (K+4)-th, . . . frames. The data signals are read from the storage medium plane A in arbitrary (K+1)-th, (K+3)-th, (K+5)-th, . . . frames in an order which is identical to that shown in FIG. 20. Similarly, the data signals are stored in the storage medium plane B in the arbitrary (K+1)-th, (K+3)-th, (K+5)-th, . . . frames in an order which is identical to that shown in FIG. 19.
In the arbitrary K-th frame, only writing of the data signals is carried out with respect to the plane A, while only reading of the data signals is carried out with respect to the plane B. In the next arbitrary (K+1)-th frame, the data are read from the plane A in which the data have been written in the K-th frame, and data writing is carried out in the plane B. De-interleaving for one frame is completed with an operation for two frames, so that it is possible to sequence (de-interleave) the order of the data signals DIN shown in FIG. 16 to that shown in FIG. 17. Following the (K+2)-th frame, the operations in the K-th and (K+1)-th frames are repeated.
Referring again to FIG. 15, operations of the respective blocks are now described. The clocks CLK, which are pulses synchronized with the data signals DIN, are inputted in the counter circuit 2 from the clock input terminal 1. The counter circuit 2 outputs address signals for the storage media 5a and 5b to the signal selection circuit 4. The counter circuit 3 detects that the counter circuit 2 completes counting of the clocks CLK for one frame, and counts the frame number. The signal selection circuit 4 switches connection between the output of the counter circuit 2 and address signal inputs of the storage media 5a and 5b in accordance with the address order shown in FIG. 18 along the output of the counter circuit 3, so that the storage media 5a and 5b can be addressed in the orders shown in FIGS. 19 and 20.
A plane in which the data signals are written is supplied with addresses in order of 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30 and 31. A plane from which the data signals are read is supplied with addresses in order of 0, 4, 8, 12, 16, 20, 24, 28, 1, 5, 9, 13, 17, 21, 25, 29, 2, 6, 10, 14, 18, 22, 26, 30, 3, 7, 11, 15, 19, 23, 27 and 31.
A data input terminal 6 inputs data signals DIN not yet de-interleaved. A READ/WRITE switching signal input terminal 7 supplies a control signal R/W for properly selecting operation modes of the planes A and B to either reading or writing.
Since either the plane A or B outputs de-interleaved data signals DOUT, an output selector 9 properly selects either output, so that the de-interleaved data signals DOUT are outputted from a data output terminal 8.
Thus, the conventional de-interleaver must be equipped with two storage medium planes each of which has storage capacity for one frame, since the operation modes of the two storage medium planes are alternately switched between write and read modes every frame for carrying out a de-interleaving operation. This also applies to a conventional interleaver.